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publication number 27552 revision b amendment +1 issue date january 23, 2006 am29lv6402m data sheet retired product this product has been retired and is not ava ilable for designs. for new and current designs, s29gl128n supersedes am29lv6402m and is the factory-recommended migration path. please refer to the s29gl128n data sheet for specifications and ordering information. availability of this document is retained for refere nce and historical purposes only july 2003 the following document specifies spansion memory products that are now o ffered by both advanced micro devices and fujitsu. althou gh the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. fu ture routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
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publication# 27552 rev: b amendment/ 1 issue date: january 23, 2006 refer to amd?s website (www.amd.com) for the latest information. am29lv6402m 128 megabit (4 m x 32-bit/8 m x 16-bit) mirrorbit ? 3.0 volt-only uniform sector flash memory with versatile i/o? control distinctive characteristics architectural advantages single power supply operation ? 3 volt read, erase, and program operations versatilei/o tm control ? device generates data output voltages and tolerates data input voltages on the ce# and dq inputs/outputs as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v manufactured on 0.23 m mirrorbit tm process technology secsi ? (secured silicon) sector region ? 128-doubleword/256-word sector for permanent, secure identification through an 8-doubleword/16-word random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer flexible sector architecture ? one hundred twenty-eight 32 kdoubleword (64 kword) sectors compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection 100,000 erase cycles per sector 20-year data retention at 125 c performance characteristics high performance ? 100 ns access time ? 30 ns page read times ? 0.5 s typical sector erase time ? 22 s typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates ? 4-doubleword/8-word page read buffer ? 16-doubleword/32-word write buffer low power consumption (typical values at 3.0 v, 5 mhz) ? 26 ma typical active read current ? 100 ma typical erase/program current ? 2 a typical standby mode current package options ? 80-ball fortified bga software & hardware features software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interface) compliant: allows host system to identify and ac commodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system produc tion. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion this product has been retired and is not available for designs. for new and current designs, s29gl128n supersedes am29lv6402m a nd is the factory-recommended migration path. please refer to the s29gl128n data sheet for spec ifications and ordering information. availabilit y of this document is retained for reference a nd historical purposes only .
2 am29lv6402m january 23, 2006 general description the am29lv6402m consists of two 64 mbit, 3.0 volt single power supply flash memory devices and is or- ganized as 4,194,304 doublewords or 8,388,608 words. the device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the word# input. the device can be programmed either in the host system or in standard eprom program- mers. an access time of 100 or 110 ns is available. note that each access time has a specific operating voltage range (v cc ) as specified in the product selector guide and the ordering information sections. the device is offered in an 80-ball fortified bga package. each de- vice has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 and dq15 (data# polling) or dq6 and dq14 (toggle) status bits or monitor the ready/busy# (ry/by#) outputs to determine whether the operation is complete. to facilitate programming, an unlock by- pass mode reduces command sequence overhead by requiring only two write cycle s to program data instead of four. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the ce# control input and dq i/os to the same voltage level that is asserted on the v io pin. refer to the ordering information section for valid v io options. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program sus- pend/program resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-doubleword/256-word area for code or data that can be permanently protected. once this sector is pro- tected, no further changes within the sector can occur. the write protect (wp# /acc ) feature protects the first or last sector by asserting a logic low on the wp# pin. amd mirrorbit tm flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection. related documents for a comprehensive information on mirrorbit prod- ucts, including migration information, data sheets, ap- plication notes, and software drivers, please see www.amd.com flash memory product informa- tion mirrorbit flash information technical docu- mentation. the following is a partial list of documents closely related to this product: mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices migrating from single-byte to three-byte device ids
january 23, 2006 am29lv6402m 3 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 flash memory block diagram . . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 special package handling instructions .................................... 6 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 x16 mode .................................................................................. 7 x32 mode .................................................................................. 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . 9 table 1. device bus operations ....................................................... 9 versatileio tm (v io ) control ........................................................ 9 requirements for reading array data ................................... 10 page mode read ............................................................................10 writing commands/command sequences ............................ 10 write buffer .....................................................................................10 accelerated program operation ......................................................10 autoselect functions .......................................................................10 automatic sleep mode ........................................................... 11 reset#: hardware reset pin ............................................... 11 output disable mode .............................................................. 11 table 2. sector address table........................................................ 12 table 3. autoselect codes, (high voltage method) ....................... 15 sector group protection and unprotection ............................. 16 table 4. sector group protection/unprotection address table ..... 16 temporary sector group unprotect ....................................... 17 figure 1. temporary sector group unprotect operation ................17 figure 2. in-system sector group protect/unprotect algorithms ...18 secsi (secured silicon) sect or flash memory region .......... 19 table 5. secsi sector contents ...................................................... 19 figure 3. secsi sector protect verify ..............................................20 hardware data protection ...................................................... 20 low vcc write inhibit .....................................................................20 write pulse ?glitch? protection ........................................................20 logical inhibit ..................................................................................20 power-up write inhibit ....................................................................20 common flash memory interface (cfi) . . . . . . . 20 table 6. cfi query identification string ..........................................21 table 7. system interface string..................................................... 21 table 8. device geometry definition ..............................................22 table 9. primary vendor-specific extended query ........................23 command definitions . . . . . . . . . . . . . . . . . . . . . 24 reading array data ................................................................ 24 reset command ..................................................................... 24 autoselect command sequence ............................................ 24 enter secsi sector/exit secsi sector command sequence .. 25 doubleword/word program command sequence ................. 25 unlock bypass command sequence ..............................................25 write buffer programming ...............................................................25 accelerated program ......................................................................26 figure 4. write buffer programming operation ...............................27 figure 5. program operation ..........................................................28 program suspend/program resume command sequence ... 28 figure 6. program suspend/program resume ...............................28 chip erase command sequence ........................................... 29 sector erase command sequence ........................................ 29 erase suspend/erase resume commands ........................... 29 figure 7. erase operation .............................................................. 30 table 10. command definitions (x32 mode, word# = v ih ) ......... 31 table 11. command definitions (x16 mode, word# = v il ).......... 32 write operation status . . . . . . . . . . . . . . . . . . . . . 33 dq7 and dq5: data# polling .................................................. 33 figure 8. data# polling algorithm .................................................. 33 dq6 and dq14: toggle bits i ................................................. 34 figure 9. toggle bit algorithm ........................................................ 35 dq2 and dq10: toggle bits ii ................................................ 35 reading toggle bits dq6 and dq14/dq2 and dq10 ............ 35 dq5 and dq13: exceeded timing limits ............................... 36 dq3 and dq11: sector erase timer ...................................... 36 dq1: write-to-buffer abort ..................................................... 37 table 12. write operation status................................................... 37 absolute maximum ratings. . . . . . . . . . . . . . . . . 38 figure 10. maximum negative overshoot waveform ................... 38 figure 11. maximum positive overshoot waveform ..................... 38 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. test setup ..................................................................... 40 table 13. test specifications ......................................................... 40 key to switching waveforms. . . . . . . . . . . . . . . . 40 figure 13. input waveforms and measurement levels ...................................................................... 40 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 read-only operations ........................................................... 41 figure 14. read operation timings ............................................... 41 figure 15. page read timings ...................................................... 42 hardware reset (reset#) .................................................... 43 figure 16. reset timings ............................................................... 43 erase and program operations .............................................. 44 figure 17. program operation timings .......................................... 45 figure 18. accelerated program timing diagram .......................... 45 figure 19. chip/sector erase operation timings .......................... 46 figure 20. data# polling timings (during embedded algorithms) . 47 figure 21. toggle bit timings (during embedded algorithms) ...... 48 figure 22. dq2 vs. dq6 ................................................................. 48 temporary sector unprotect .................................................. 49 figure 23. temporary sector group unprotect timing diagram ... 49 figure 24. sector group protect and unprotect timing diagram .. 50 alternate ce# controlled erase and program operations ..... 51 figure 25. alternate ce# controlled write (erase/program) operation timings .......................................................................... 52 latchup characteristics . . . . . . . . . . . . . . . . . . . . 52 erase and programming performance. . . . . . . . 53 tsop pin and bga package capacitance . . . . . 53 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 lsb080?80-ball fortified ball grid array (fortified bga) 13 x 11 mm package .............................................................. 54 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 55
4 am29lv6402m january 23, 2006 product selector guide mcp block diagram note: in x16 mode, dq31 and dq23 must be connected together on the board. part number am29lv1282m speed option v cc = 3.0?3.6 v 100r (v io = 2.7?3.6 v) 110r (v io = 1.65?3.6 v) max. access time (ns) 100 110 max. ce# access time (ns) 100 110 max. page access time (t pac c )3030 max. oe# access time (ns) 30 30 oe# we# ce# 64 mbit flash memory #2 64 mbit flash memory #1 dq23/a-1 to dq16; dq7-dq0 dq31/a-1 to dq24; dq15 to dq8 dq31 to dq0 a21 to a0 ry/by# reset# x16 x16 x32 word# wp#/acc
january 23, 2006 am29lv6402m 5 flash memory block diagram note: in x16 mode, dq31 and dq23 must be connected together on the board. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc word# ce# oe# stb stb dq31 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a21?a0 v io
6 am29lv6402m january 23, 2006 connection diagrams note: the fbga package pinout configuration show n is preliminary. the ball count and package physical dimensions have not yet been determined. contact amd for further information. special package ha ndling instructions special handling is required for flash memory products in molded packages (t sop, bga, plcc, pdip, ssop). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 word# dq15 a16 a15 a14 a12 a13 dq23/a-1 dq14 dq13 dq7 a11 a10 a8 a9 dq30 dq12 v cc dq5 a19 a21 reset# we# v ss dq10 dq11 dq2 a20 a18 wp#/acc ry/by# v cc dq8 dq9 dq0 a5 a6 a17 a7 dq31/a-1 ce# oe# a0 a1 a2 a4 a3 dq18 a1 c1 d1 e1 f1 g1 h1 v io rfu rfu rfu rfu v cc dq16 rfu a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 rfu rfu j2 j3 j4 j5 j6 j7 v ss dq6 dq4 dq3 dq1 v ss j1 dq24 j8 dq29 k2 k3 k4 k5 k6 k7 dq20 dq27 dq26 dq19 dq17 v cc k1 dq25 k8 dq22 v ss v io rfu rfu dq28 dq21 80-ball fortified bga top view, balls facing down
january 23, 2006 am29lv6402m 7 pin configuration a ?1 = least significant address bit for the 16-bit data bus, and selects between the high and low word. a ?1 is not used for the 32-bit mode (word# = v ih ). a21?a0 = 22-bit address bus for 128 mb device. dq31?dq0 = 32-bit data inputs/outputs/float word# = selects 16-bit or 32-bit mode. when word# = v ih , data is output on dq31?dq0. when word# = v il , data is output on dq15?dq0. ce# = chip enable input. oe# = output enable input. we# = write enable. v ss = device ground ry/by# = ready/busy output and open drain. when ry/by# = v oh , the device is ready to ac- cept read operations and commands. when ry/by# = v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset oper- ation. wp#/acc = write protect input/acceleration input. v cc = power supply (2.7 v to 3.6 v) reset# = hardware reset input nc = pin not connected internally logic symbols x16 mode x32 mode note: in x16 mode, dq31 and dq23 must be connected to each other on the board. 23 16 dq15?dq0 a21 to a-1 ry/by# ce# oe# we# wp#/acc reset# wp# word# v io 22 32 dq31?dq0 a21?a0 ry/by# ce# oe# we# wp#/acc reset# wp# word# v io
8 am29lv6402m january 23, 2006 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configur ations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of s pecific valid combinations and to check on newly re- leased combinations. am29lv6402m h 100r ph i temperature range i = industrial (?40 c to +85 c) package type ph = 80-ball fortified ball grid array ( f bga), 1.00 mm ball pitch, 13 x 11 mm, (lsb080) speed option see product selector guide and valid combinations sector architecture and sector write protection (wp# = v il ) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv6402mh/l 2 x 64 megabit (4 m x 32-bit/8 m x 16-bit) mirrorbit tm uniform sector flash memory 3.0 volt-only read, program, and erase valid combinations for fortified bga package speed (ns) v cc range v io range order number package marking am29lv6402mh100r, am29lv6402ml100r phi l6402mh10r i 100 3.0? 3.6 v 2.7? 3.6 v am29lv6402mh110r, am29lv6402ml110r phi l6402ml11r i 110 1.65? 3.6 v
january 23, 2006 am29lv6402m 9 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0 in doubleword mode; a21:a-1 in word mode. sector addresses are a21:a15 in both modes. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector re mains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?sector group protection and unprotection?. all sectors are unprotected when shipped from the factory (the secsi sector may be fa ctory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). word/byte configuration the word# pin controls whether the device data i/o pins operate in the word or doubleword configuration. if the word# pin is set at v ih , the device is in double- word configuration, dq31?dq0 are active and con- trolled by ce# and oe#. if the word# pin is set at v il , the device is in word configuration, and only data i/o pins dq15?dq0 are active and controlled by ce# and oe#. the data i/o pins dq31?dq16 are tri-stated, and the dq23 and dq31 pins are used as inputs for the lsb (a-1) ad- dress function. versatileio tm (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ordering information for v io options on this device. operation ce# oe# we# reset# wp# acc addresses (note 2) dq15? dq0 dq31?dq16 word# = v ih word# = v il read l l h h xx a in d out d out dq31?dq16 = high-z, dq31 & dq23= a-1 write (program/erase) l h l h (note 3) x a in (note 4) (note 4) accelerated program l h l h (note 3) v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v xh x high-z high-z high-z output disable l h h h xx x high-z high-z high-z reset x x x l xx x high-z high-z high-z sector group protect (note 2) lhlv id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) x x sector group unprotect (note 2) lhlv id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) x x temporary sector group unprotect xxxv id hx a in (note 4) (note 4) high-z
10 am29lv6402m january 23, 2006 requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing speci- fications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 doublewords/8 words. the appropriate page is selected by the higher address bits a(max)?a2. address bits a1?a0 in doubleword mode (a1?a-1 in word mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?doubleword/word program command sequence? section has details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 doublewords/32 words in one pro- gramming operation. this results in faster effective programming time than the standard programming al- gorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. wp# has an inter- nal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autose lect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not read ing or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than
january 23, 2006 am29lv6402m 11 v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 16 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
12 am29lv6402m january 23, 2006 table 2. sector address table sector a21?a15 sector size (kwords/kdoublewords) 16-bit address range (in hexadecimal) 32-bit address range (in hexadecimal) sa0 0000000 64/32 000000?00ffff 000000?007fff sa1 0000001 64/32 010000?01ffff 008000?00ffff sa2 0000010 64/32 020000?02ffff 010000?017fff sa3 0000011 64/32 030000?03ffff 018000?01ffff sa4 0000100 64/32 040000?04ffff 020000?027fff sa5 0000101 64/32 050000?05ffff 028000?02ffff sa6 0000110 64/32 060000?06ffff 030000?037fff sa7 0000111 64/32 070000?07ffff 038000?03ffff sa8 0001000 64/32 080000?08ffff 040000?047fff sa9 0001001 64/32 090000?09ffff 048000?04ffff sa10 0001010 64/32 0a000 0?0affff 050000?057fff sa11 0001011 64/32 0b000 0?0bffff 058000?05ffff sa12 0001100 64/32 0c000 0?0cffff 060000?067fff sa13 0001101 64/32 0d000 0?0dffff 068000?06ffff sa14 0001110 64/32 0e000 0?0effff 070000?077fff sa15 0001111 64/32 0f000 0?0fffff 078000?07ffff sa16 0010000 64/32 100000?10ffff 080000?087fff sa17 0010001 64/32 110000?11ffff 088000?08ffff sa18 0010010 64/32 120000?12ffff 090000?097fff sa19 0010011 64/32 130000?13ffff 098000?09ffff sa20 0010100 64/32 140000?14ffff 0a0000?0a7fff sa21 0010101 64/32 150000?15ffff 0a8000?0affff sa22 0010110 64/32 160000?16ffff 0b0000?0b7fff sa23 0010111 64/32 170000?17ffff 0b8000?0bffff sa24 0011000 64/32 180000?18ffff 0c0000?0c7fff sa25 0011001 64/32 190000?19ffff 0c8000?0cffff sa26 0011010 64/32 1a000 0?1affff 0d0000?0d7fff sa27 0011011 64/32 1b000 0?1bffff 0d8000?0dffff sa28 0011100 64/32 1c000 0?1cffff 0e0000?0e7fff sa29 0011101 64/32 1d000 0?1dffff 0e8000?0effff sa30 0011110 64/32 1e000 0?1effff 0f0000?0f7fff sa31 0011111 64/32 1f000 0?1fffff 0f8000?0fffff sa32 0100000 64/32 020 0000?20ffff 100000?107fff sa33 0100001 64/32 210000?21ffff 108000?10ffff sa34 0100010 64/32 220000?22ffff 110000?117fff sa35 0100011 64/32 230000?23ffff 118000?11ffff sa36 0100100 64/32 240000?24ffff 120000?127fff sa37 0100101 64/32 250000?25ffff 128000?12ffff sa38 0100110 64/32 260000?26ffff 130000?137fff sa39 0100111 64/32 270000?27ffff 138000?13ffff sa40 0101000 64/32 280000?28ffff 140000?147fff sa41 0101001 64/32 290000?29ffff 148000?14ffff sa42 0101010 64/32 2a000 0?2affff 150000?157fff sa43 0101011 64/32 2b000 0?2bffff 158000?15ffff sa44 0101100 64/32 2c000 0?2cffff 160000?167fff sa45 0101101 64/32 2d000 0?2dffff 168000?16ffff sa46 0101110 64/32 2e000 0?2effff 170000?177fff
january 23, 2006 am29lv6402m 13 sa47 0101111 64/32 2f000 0?2fffff 178000?17ffff sa48 0110000 64/32 300000?30ffff 180000?187fff sa49 0110001 64/32 310000?31ffff 188000?18ffff sa50 0110010 64/32 320000?32ffff 190000?197fff sa51 0110011 64/32 330000?33ffff 198000?19ffff sa52 0110100 64/32 340000?34ffff 1a0000?1a7fff sa53 0110101 64/32 350000?35ffff 1a8000?1affff sa54 0110110 64/32 360000?36ffff 1b0000?1b7fff sa55 0110111 64/32 370000?37ffff 1b8000?1bffff sa56 0111000 64/32 380000?38ffff 1c0000?1c7fff sa57 0111001 64/32 390000?39ffff 1c8000?1cffff sa58 0111010 64/32 3a000 0?3affff 1d0000?1d7fff sa59 0111011 64/32 3b000 0?3bffff 1d8000?1dffff sa60 0111100 64/32 3c000 0?3cffff 1e0000?1e7fff sa61 0111101 64/32 3d000 0?3dffff 1e8000?1effff sa62 0111110 64/32 3e000 0?3effff 1f0000?1f7fff sa63 0111111 64/32 3f000 0?3fffff 1f8000?1fffff sa64 1000000 64/32 400000?40ffff 200000?207fff sa65 1000001 64/32 410000?41ffff 208000?20ffff sa66 1000010 64/32 420000?42ffff 210000?217fff sa67 1000011 64/32 430000?43ffff 218000?21ffff sa68 1000100 64/32 440000?44ffff 220000?227fff sa69 1000101 64/32 450000?45ffff 228000?22ffff sa70 1000110 64/32 460000?46ffff 230000?237fff sa71 1000111 64/32 470000?47ffff 238000?23ffff sa72 1001000 64/32 480000?48ffff 240000?247fff sa73 1001001 64/32 490000?49ffff 248000?24ffff sa74 1001010 64/32 4a000 0?4affff 250000?257fff sa75 1001011 64/32 4b000 0?4bffff 258000?25ffff sa76 1001100 64/32 4c000 0?4cffff 260000?267fff sa77 1001101 64/32 4d000 0?4dffff 268000?26ffff sa78 1001110 64/32 4e000 0?4effff 270000?277fff sa79 1001111 64/32 4f000 0?4fffff 278000?27ffff sa80 1010000 64/32 500000?50ffff 280000?287fff sa81 1010001 64/32 510000?51ffff 288000?28ffff sa82 1010010 64/32 520000?52ffff 290000?297fff sa83 1010011 64/32 530000?53ffff 298000?29ffff sa84 1010100 64/32 540000?54ffff 2a0000?2a7fff sa85 1010101 64/32 550000?55ffff 2a8000?2affff sa86 1010110 64/32 560000?56ffff 2b0000?2b7fff sa87 1010111 64/32 570000?57ffff 2b8000?2bffff sa88 1011000 64/32 580000?58ffff 2c0000?2c7fff sa89 1011001 64/32 590000?59ffff 2c8000?2cffff sa90 1011010 64/32 5a000 0?5affff 2d0000?2d7fff sa91 1011011 64/32 5b000 0?5bffff 2d8000?2dffff sa92 1011100 64/32 5c000 0?5cffff 2e0000?2e7fff sa93 1011101 64/32 5d000 0?5dffff 2e8000?2effff sa94 1011110 64/32 5e000 0?5effff 2f0000?2f7fff table 2. sector address table (continued) sector a21?a15 sector size (kwords/kdoublewords) 16-bit address range (in hexadecimal) 32-bit address range (in hexadecimal)
14 am29lv6402m january 23, 2006 sa95 1011111 64/32 5f000 0?5fffff 2f8000?2fffff sa96 1100000 64/32 600000?60ffff 300000?307fff sa97 1100001 64/32 610000?61ffff 308000?30ffff sa98 1100010 64/32 620000?62ffff 310000?317fff sa99 1100011 64/32 630000?63ffff 318000?31ffff sa100 1100100 64/32 640000?64ffff 320000?327fff sa101 1100101 64/32 650000?65ffff 328000?32ffff sa102 1100110 64/32 660000?66ffff 330000?337fff sa103 1100111 64/32 670000?67ffff 338000?33ffff sa104 1101000 64/32 680000?68ffff 340000?347fff sa105 1101001 64/32 690000?69ffff 348000?34ffff sa106 1101010 64/32 6a000 0?6affff 350000?357fff sa107 1101011 64/32 6b000 0?6bffff 358000?35ffff sa108 1101100 64/32 6c000 0?6cffff 360000?367fff sa109 1101101 64/32 6d000 0?6dffff 368000?36ffff sa110 1101110 64/32 6e000 0?6effff 370000?377fff sa111 1101111 64/32 6f000 0?6fffff 378000?37ffff sa112 1110000 64/32 700000?70ffff 380000?387fff sa113 1110001 64/32 710000?71ffff 388000?38ffff sa114 1110010 64/32 720000?72ffff 390000?397fff sa115 1110011 64/32 730000?73ffff 398000?39ffff sa116 1110100 64/32 740000?74ffff 3a0000?3a7fff sa117 1110101 64/32 750000?75ffff 3a8000?3affff sa118 1110110 64/32 760000?76ffff 3b0000?3b7fff sa119 1110111 64/32 770000?77ffff 3b8000?3bffff sa120 1111000 64/32 780000?78ffff 3c0000?3c7fff sa121 1111001 64/32 790000?79ffff 3c8000?3cffff sa122 1111010 64/32 7a000 0?7affff 3d0000?3d7fff sa123 1111011 64/32 7b000 0?7bffff 3d8000?3dffff sa124 1111100 64/32 7c000 0?7cffff 3e0000?3e7fff sa125 1111101 64/32 7d000 0?7dffff 3e8000?3effff sa126 1111110 64/32 7e000 0?7effff 3f0000?3f7fff sa127 1111111 64/32 7f000 0?7fffff 3f8000?3fffff table 2. sector address table (continued) sector a21?a15 sector size (kwords/kdoublewords) 16-bit address range (in hexadecimal) 32-bit address range (in hexadecimal)
january 23, 2006 am29lv6402m 15 autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-syste m through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table 3. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 3 shows the remain- ing address bits that are don?t care. when all neces- sary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in tables 10 and 11 . this method does not require v id . refer to the autoselect command sequence section for more information. table 3. autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a21 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq23 to dq16 dq7 to dq0 word# = v ih word# = v il manufacturer id : amd l l h x x v id x l x l l l 00 x 01h device id cycle 1 llhxx v id xl x llh 22 x 7eh cycle 2 h h l 22 x 0ch cycle 3 h h h 22 x 01h sector protection verification llhsax v id xl x l h l x x 01h (protected), 00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector llhxx v id xl x l h h x x 98h (factory locked), 18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector llhxx v id xl x l h h x x 88h (factory locked), 08h (not factory locked)
16 am29lv6402m january 23, 2006 sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see table 4). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the re- set# pin only, and can be implemented either in-sys- tem or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing dia- gram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and pro- tecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. con- tact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 4. sector group protection/unprotection address table sector group a21?a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4?sa7 00001xx sa8?sa11 00010xx sa12?sa15 00011xx sa16?sa19 00100xx sa20?sa23 00101xx sa24?sa27 00110xx sa28?sa31 00111xx sa32?sa35 01000xx sa36?sa39 01001xx sa40?sa43 01010xx sa44?sa47 01011xx sa48?sa51 01100xx sa52?sa55 01101xx sa56?sa59 01110xx sa60?sa63 01111xx sa64?sa67 10000xx sa68?sa71 10001xx sa72?sa75 10010xx sa76?sa79 10011xx sa80?sa83 10100xx sa84?sa87 10101xx sa88?sa91 10110xx sa92?sa95 10111xx sa96?sa99 11000xx sa100?sa103 11001xx sa104?sa107 11010xx sa108?sa111 11011xx sa112?sa115 11100xx sa116?sa119 11101xx sa120?sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111
january 23, 2006 am29lv6402m 17 write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector without using v id . write protect is one of two functions pro- vided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method de- scribed in ?sector group protection and unprotection?. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc characteristics?. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the fi rst or last sector was pre- viously set to be protected or unprotected using the method described in ?sector group protection and unprotection?. note that wp# has an internal pullup; when unconnected, wp# is at v ih . temporary sector group unprotect note: in this device, a sector group consists of four ad- jacent sectors that are protected or unprotected at the same time (see figure 5). this feature allows tempo- rary unprotection of previously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 1 shows the algorithm, and figure 23 shows the timing dia- grams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
18 am29lv6402m january 23, 2006 figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6 = 0, a1 = 1, a0 = 0 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address twith a6 = 0, a1 = 1, a0 = 0 read from sector group address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6 = 1, a1 = 1, a0 = 0 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6 = 1, a1 = 1, a0 = 0 read from sector group address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
january 23, 2006 am29lv6402m 19 secsi (secured sili con) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 doublewords/256 words in length, and uses secsi sector indicator bits (dq7 and dq15) to indicate whether or not the secsi sector is locked when shipped from the factory. these bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bits permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to program the sector after receiving the device. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bits prevent customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address spac e in this device is allo- cated as follows: table 5. secsi sector contents the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. a factory locked device has an 8-doubleword/16-word random esn at addresses 000000h?000007h. customers may opt to have their code programmed by amd through the amd expre ssflash service. the de- vices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protected at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-doubleword/256 word secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see to reduce power consumption read lower byte only.. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is on ly applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. secsi sector address range standard factory locked expressflash factory locked customer lockable x32 x16 000000h? 000007h 000000h? 00000fh esn esn or determined by customer determined by customer 000008h? 00007fh 000010h? 0000ffh unavailable determined by customer
20 am29lv6402m january 23, 2006 figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 10 and 11 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cf i query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the device to the autoselect mode. for further information, plea se refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/over- view/cfi.html. alternatively, contact an amd represen- tative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
january 23, 2006 am29lv6402m 21 table 6. cfi query identification string table 7. system interface string addresses (x32) data description 10h 11h 12h 00005151h 00005252h 00005959h query unique ascii string ?qry? 13h 14h 00000202h 00000000h primary oem command set 15h 16h 00004040h 00000000h address for primary extended table 17h 18h 00000000h 00000000h alternate oem command set (00h = none exists) 19h 1ah 00000000h 00000000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 00002727h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 00003636h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 00000000h v pp min. voltage (00h = no v pp pin present) 1eh 00000000h v pp max. voltage (00h = no v pp pin present) 1fh 00000707h typical timeout per single byte/word write 2 n s 20h 00000707h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 00000a0ah typical timeout per individual block erase 2 n ms 22h 00000000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 00000101h max. timeout for byte/word write 2 n times typical 24h 00000505h max. timeout for buffer write 2 n times typical 25h 00000404h max. timeout per individual block erase 2 n times typical 26h 00000000h max. timeout for full chip erase 2 n times typical (00h = not supported)
22 am29lv6402m january 23, 2006 table 8. device geometry definition addresses (x16) data description 27h 00001717h device size = 2 n byte 28h 29h 00000101h 00000000h flash device interface description (refer to cfi publication 100) 2ah 2bh 00000505h 00000000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 00000101h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 00007f7fh 00000000h 00000000h 00000101h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 00000000h 00000000h 00000000h 00000000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 00000000h 00000000h 00000000h 00000000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 00000000h 00000000h 00000000h 00000000h erase block region 4 information (refer to cfi publication 100)
january 23, 2006 am29lv6402m 23 table 9. primary vendor-specific extended query note: to reduce power consumption read lower byte only. addresses (x16) data description 40h 41h 42h 00005050h 00005252h 00004949h query-unique ascii string ?pri? 43h 00003131h major version number, ascii 44h 00003333h minor version number, ascii 45h 000000808h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 000000202h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 00000101h sector protect 0 = not supported, x = number of sectors in per group 48h 00000101h sector temporary unprotect 00 = not supported, 01 = supported 49h 00000404h sector protect/ unprotect scheme 04 = 29lv800 mode 4ah 00000000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 00000000h burst mode type 00 = not supported, 01 = supported 4ch 00000101h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0000b5b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0000c5c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00000404h/ 00000505h top/bottom boot sector flag 00h = uniform device without wp# protec t, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 00000101h program suspend 00h = not supported, 01h = supported
24 am29lv6402m january 23, 2006 command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. tables 10 and 11 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to read- ing array data. all addresses are latched on the falling edge of we# or ce#, whichever happens la ter. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section fo r more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 or dq13 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an aut oselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 or dq13 goes high during a program or erase operation, writing the reset command returns the de- vice to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 or dq9 goes high during a write buffer programming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 11 shows the address and data requirements. this method is an alternative to that shown in table 3, which is intended for prom programmers and re- quires v id on address pin a9. the autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: a read cycle at address xx00h returns the manu- facturer code. three read cycles at addresses 01h, 0eh, and 0fh return the device code. a read cycle to an address containing a sector ad- dress (sa), and the address 02h on a7?a0 in dou- bleword mode returns 0101h if the sector is protected, or 0000h if it is unprotected. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend).
january 23, 2006 am29lv6402m 25 enter secsi sector/e xit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-doubleword/16-word random elec- tronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector com- mand sequence. the exit secsi sector command se- quence returns the device to normal operation. tables 10 and 11 show the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash memory region? for further infor- mation. doubleword/word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 10 and 11 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 and dq15 or dq6 and dq14. refer to the write operation status section for information on these sta- tus bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 and/or dq13 = 1, or cause the dq7 and/or dq15, and dq6 and/or dq14 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 2020h. the device then enters the unlock bypass mode. a two-cy- cle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0a0h; the second cycle contains the pro- gram address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. tables 10 and 11 show the re- quirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 9090h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 doublewords/32 words in one pro- gramming operation. this results in faster effective programming time than the standard programming al- gorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector ad- dress in which programming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for ex- ample, if the system will pr ogram 6 unique address lo- cations, then 0505h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a23?a4. all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sector s. if the system attempts
26 am29lv6402m january 23, 2006 to load programming data outside of the selected write-buffer page, th e operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter dec- rements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last add ress location loaded into the write buffer. dq7 and dq15, dq6 and dq14, dq5 and dq13, and dq1 and dq9 should be monitored to determine the device status during write buffer pro- gramming. the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 and dq9 = 1, dq7 and dq15 = data# (for the last address location loaded), dq6 and dq14 = toggle, and dq5 and dq13 =0. a write-to-buffer-abort reset command sequence must be written to reset the device for the next opera- tion. note that the full 3-cycle write-to-buffer-abort reset command sequence is required when using write-buffer-programming features in unlock bypass mode. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 and/or dq13= 1, or cause the dq7 and/or dq15 and dq6 and/or dq14 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when un- connected, wp# is at v ih . figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
january 23, 2006 am29lv6402m 27 figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 and dq15 may change simultaneously with dq5 and dq13. therefore, dq7 and dq15 should be verified. 3. if this flowchart location was reached because dq5 and dq13 = ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1 and dq9 =1, write the write-buffer-programming-abort-reset command. if dq5 and dq13 =1, write the reset command. 4. see tables 10 and 11 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
28 am29lv6402m january 23, 2006 figure 5. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 15 s max (5 s typical) and updates the status bits. ad- dresses are not required when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. the system may also writ e the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can deter- mine the status of the program operation using the dq7 and dq15 or dq6 and dq14 status bits, just as in the standard program operation. see write opera- tion status for more information. the system must write th e program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. figure 6. program suspend/program resume start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see tables 10 and 11 for program command sequence. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
january 23, 2006 am29lv6402m 29 chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initia ted by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. tables 10 and 11 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 and dq15, dq6 and dq14, or dq2 and dq10. refer to the write op- eration status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characterist ics section for parameters, and figure 19 section for timing diagrams. sector erase co mmand sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 11 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must re- write the command sequence and any additional ad- dresses and commands. the system can monitor dq3 and dq11 to determine if the sector erase timer has timed out (see the section on dq3 and dq11: sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing sector. the system can de- termine the status of the erase operation by reading dq7 and dq15, dq6 and dq14, or dq2 and dq10 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 7 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum of 20 s) to suspend the erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.
30 am29lv6402m january 23, 2006 after the erase operation has been suspended, the device enters the erase-su spend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq15?dq0. the system can use dq7 and dq15, or dq6 and dq14 and dq2 and dq10 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write op- eration status section for information on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 and dq15 or dq6 and dq14 status bits, just as in the standard word pro- gram operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 7. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see tables 10 and 11 for program command sequence. 2. see the section on dq3 and dq10 for information on the sector erase timer.
january 23, 2006 am29lv6402m 31 command definitions table 10. command definitions (x32 mode, word# = v ih ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. dwc = doubleword count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq31?dq16 are don?t care in command sequences, except for rd, pd, and dwc. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 and/or dq13 goes high while the device is providing status information. 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq31?dq16 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. if wp# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. if wp# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked. 11. the total number of cycles in the command sequence is determined by the number of doublewords written to the write buffer. the maximum number of cycles in the command sequence is 21. 12. the data is 0000h for an unprotected sector and 0101h for a protected sector. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0f0 autoselect (note 8) manufacturer id 4 555 aaaa 2aa 5555 555 9090 x00 00000101 device id (note 9) 6 555 aaaa 2aa 5555 555 9090 x01 2222 7e7e x0e 2222 0c0c x0f 2222 0101 secsi tm sector factory protect (note 10) 4 555 aaaa 2aa 5555 555 9090 x03 (note 10) sector protect verify (note 12) 4 555 aaaa 2aa 5555 555 9090 (sa)x02 0000/ 0101 enter secsi sector region 3 555 aaaa 2aa 5555 555 8888 exit secsi sector region 4 555 aaaa 2aa 5555 555 9090 xxx 0000 program 4 555 aaaa 2aa 5555 555 a0a0 pa pd write to buffer (note 11) 3 555 aaaa 2aa 5555 sa 2525 sa dwc pa pd wbl pd program buffer to flash 1 sa 2929 write to buffer abort reset (note 13) 3 555 aaaa 2aa 5555 555 f0f0 unlock bypass 3 555 aaaa 2aa 5555 555 2020 unlock bypass program (note 14) 2 xxx a0a0 pa pd unlock bypass reset (note 15) 2 xxx 9090 xxx 0000 chip erase 6 555 aaaa 2aa 5555 555 8080 555 aaaa 2aa 5555 555 1010 sector erase 6 555 aaaa 2aa 5555 555 8080 555 aaaa 2aa 5555 sa 3030 program/erase suspend (note 16) 1 xxx b0b0 program/erase resume (note 17) 1 xxx 3030 cfi query (note 18) 1 55 9898
32 am29lv6402m january 23, 2006 table 11. command definitions (x16 mode, word# = v il ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq31?dq15 are don?t care in command sequences. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 and/or dq13goes high while the device is providing status information. 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq31?dq16 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. if wp# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. if wp# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 12. the data is 0000h for an unprotected sector group and 0101h for a protected sector group. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0f0 autoselect (note 8) manufacturer id 4 aaa aaaa 555 5555 aaa 9090 x00 0101 device id (note 9) 6 aaa aaaa 555 5555 aaa 9090 x02 7e7e x1c 0c0c x1e 0101 secsi tm sector factory protect (note 10) 4 aaa aaaa 555 5555 aaa 9090 x06 (note 10) sector protect verify (note 12) 4 aaa aaaa 555 5555 aaa 9090 (sa)x04 0000/ 0101 enter secsi sector region 3 aaa aaaa 555 5555 aaa 8888 exit secsi sector region 4 aaa aaaa 555 5555 aaa 9090 xxx 0000 program 4 aaa aaaa 555 5555 aaa a0a0 pa pd write to buffer (note 11) 3 aaa aaaa 555 5555 sa 2525 sa wc pa pd wbl pd program buffer to flash 1 sa 2929 write to buffer abort reset (note 13) 3 aaa aaaa 555 5555 aaa f0f0 unlock bypass 3 aaa aaaa 555 5555 aaa 2020 unlock bypass program (note 14) 2 xxx a0a0 pa pd unlock bypass reset (note 15) 2 xxx 9090 xxx 0000 chip erase 6 aaa aaaa 555 5555 aaa 8080 aaa aaaa 555 5555 aaa 1010 sector erase 6 aaa aaaa 555 5555 aaa 8080 aaa aaaa 555 5555 sa 3030 program/erase suspend (note 16) 1 xxx b0b0 program/erase resume (note 17) 1 xxx 3030 cfi query (note 18) 1 aa 9898
january 23, 2006 am29lv6402m 33 write operation status the device provides several bits to determine the status of a program or erase operation: dq2 and dq10, dq3 and dq11, dq5 and dq13, dq6 and dq14, and dq7 and dq15. table 12 and the following subsections describe the function of these bits. dq7 and dq15 and dq6 and dq14 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been com- pleted. dq7 and dq5: data# polling the data# polling bit, dq7 and dq15, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 and dq15 the complement of the datum pro- grammed to dq7 and dq15. this dq7 and dq15 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7 and dq15. the system must provide the program address to read valid sta- tus information on dq7 and dq15. if a program address falls within a protected sector, data# polling on dq7 and dq15 is active for approximately 1 s, then the device re- turns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7 and dq15. when the embed- ded erase algorithm is complete, or if the device en- ters the erase suspend mode, data# polling produces a ?1? on dq7 and dq15. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7 and dq15. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 and dq15 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 and dq15 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 and dq15 may change asyn- chronously with dq6?dq0 and dq14?dq8 while out- put enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7 and dq15. d epending on when the sys- tem samples the dq7 and dq15 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq6?dq0 and dq14?dq8 may be still invalid. valid data on dq15?dq0 will appear on successive read cycles. table 12 shows the outputs for data# polling on dq7 and dq15. figure 8 shows the data# polling algo- rithm. figure 20 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being eras ed. during chip erase, a valid address is any non- protected sector address. 2. dq7 and dq15 should be rechecked even if dq5 and/or dq13 = ?1? because dq7 and dq15 may change simultaneously with dq5 and dq13.
34 am29lv6402m january 23, 2006 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 12 shows the outputs for ry/by#. dq6 and dq14: toggle bits i toggle bit i on dq6 and dq14 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read c ycles to any address cause dq6 and dq14 to toggle. the system may use either oe# or ce# to control the read cycles. when the oper- ation is complete, dq6 and dq14 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 and dq14 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ig- nores the selected sectors that are protected. the system can use dq6 and dq14 and dq2 and dq10 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 and dq14 toggle. when the device enters the erase sus- pend mode, dq6 and dq14 stop toggling. however, the system must also use dq2 and dq10 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 and dq15 (see the subsection on dq7 and dq15: data# polling). if a program address falls within a protected sector, dq6 and dq14 toggle for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 and dq14 also toggle during the erase-sus- pend-program mode, and stops toggling once the em- bedded program algorithm is complete. table 12 shows the outputs for toggle bit i on dq6 and dq14. figure 9 shows the toggle bit algorithm. figure 21 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 22 shows the dif- ferences between dq2 and dq10 and dq6 and dq14 in graphical form. see also the subsection on dq2 and dq10: toggle bits ii.
january 23, 2006 am29lv6402m 35 figure 9. toggle bit algorithm dq2 and dq10: toggle bits ii the ?toggle bits ii? on dq2 and dq10, when used with dq6 and dq14, indicate whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bits ii are valid after the ris- ing edge of the final we# pulse in the command se- quence. dq2 and dq10 toggle when the system reads at ad- dresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 and dq10 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6 and dq14, by comparison, in- dicate whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are re- quired for sector and mode information. refer to table 12 to compare outputs for dq2 and dq10 and dq6 and dq14. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2 and dq10: toggle bits ii? explains the algorithm. see also the ry/by#: ready/busy# subsection. figure 21 shows the toggle bit timing diagram. figure 22 shows the differences between dq2 and dq10 and dq6 and dq14 in graphical form. reading toggle bits dq6 and dq14/dq2 and dq10 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bits sta- tus, it must read dq15?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bits are not toggling, the de- vice has completed the program or erase operation. the system can read array data on dq15?dq0 on the following read cycle. however, if after the initia l two read cycles, the system determines that o ne of the toggle bits are still toggling, the system also should note whether the value of dq5 and dq13 is high (see the section on dq5 and dq13). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 and/or dq13 went high. if the toggle bits are no longer toggling, the device has successfully completed the program or erase operation. if it is st ill toggling, the device did not completed the operation su ccessfully, and the system must write the reset command to return to reading array data. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 and dq13= ?1? because the toggle bit may stop toggling as dq5 and dq13 changes to ?1.? see the subsections on dq6 and dq14 and dq2 and dq10 for more information.
36 am29lv6402m january 23, 2006 the remaining scenario is th at the system initially de- termines that the toggle bit is toggling and dq5 and/or dq13 has not gone high. the system may continue to monitor the toggle bits and dq5 and dq13 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the opera- tion (top of figure 9). dq5 and dq13: excee ded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 and dq13 produce a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 and/or dq13 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase opera- tion can change a ?0? back to a ?1.? under this con- dition, the device halts the operation, and when the timing limit has been exceeded, dq5 and/or dq13 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3 and dq11: sector erase timer after writing a sector erase command sequence, the system may read dq3 and dq11 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is com- plete, dq3 and dq11 switch from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3 and dq11. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 and dq15 (data# poll- ing) or dq6 and dq14 (toggle bits i) to ensure that the device has accepted the command sequence, and then read dq3 and dq11. if dq3 and dq11 are ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 and dq11 are ?0,? the device will accept additional sector erase com- mands. to ensure the command has been accepted, the system software should check the status of dq3 and dq11 prior to and following each subsequent sec- tor erase command. if dq3 and dq11 are high on the second status check, the last command might not have been accepted. table 12 shows the status of dq3 and dq11 relative to the other status bits.
january 23, 2006 am29lv6402m 37 dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 and dq9 produce a ?1?. the sy stem must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer programming section for more details. table 12. write operation status notes: 1. dq5 and dq13 switch to ?1? when an embedded program, embedd ed erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 and dq13 for more information. 2. dq7 and dq15 and dq2 and dq10 require a valid address when readin g status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 and dq9 switch to ?1? when the devi ce has aborted the write-to-buffer operation. status dq7/dq15 (note 2) dq6/dq14 dq5/ da13 (note 1) dq3/ dq11 dq2/dq10 (note 2) dq1/ dq9 ry/by# standard mode embedded program algorithm dq7/da15# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7/dq15# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7/dq15# toggle 0 n/a n/a 0 0 abort (note 4) dq7/dq15# toggle 0 n/a n/a 1 0
38 am29lv6402m january 23, 2006 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . ?55c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, wp#/acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, wp#/acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0?3.6 v v io (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 1.65?3.6 v 4. operating ranges define those limits between which the functionality of the device is guaranteed. 5. see ordering information for valid vcc/vio combinations. the i/os will not operate at 3 v when v io = 1.8 v 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
january 23, 2006 am29lv6402m 39 dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 10.0 a. 2. the i cc current listed is typically less than 4 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 2.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 70 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 2.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih , 1 mhz 6 68 ma 5 mhz 26 86 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 1 mhz 8 100 ma 10 mhz 80 160 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 mhz 6 40 ma 33 mhz 12 80 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 100 120 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 210a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 210a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 210a v il input low voltage ?0.5 0.8 v v ih input high voltage 1.9 v io + 0.3 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.4 v i ol = 100 a, v cc = v cc min 0.1 v v oh output high voltage i oh = ?2.0 ma, v cc = v cc min 2.4 v i oh = ?100 a, v cc = v cc min v cc ? 0.1 v lko low v cc lock-out voltage (6) 2.3 2.5 v
40 am29lv6402m january 23, 2006 test conditions table 13. test specifications key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t note: diodes are in3064 or equivalent. figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input figure 13. input waveforms and measurement levels
january 23, 2006 am29lv6402m 41 ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specif ications. 3. ac specifications are tested with v io =v cc . please contact the factory for information on using the device with v io v cc . parameter description test setup speed options jedec std. 100r 110r unit t avav t rc read cycle time (note 1) min 100 110 ns t avqv t acc address to output delay ce#, oe# = v il max 100 110 ns t elqv t ce chip enable to output delay oe# = v il max 100 110 ns t pac c page access time max 30 30 ns t glqv t oe output enable to output delay max 30 30 ns t ehqz t df chip enable to output high z (note 1) max 25 ns t ghqz t df output enable to output high z (note 1) max 25 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
42 am29lv6402m january 23, 2006 ac characteristics * figure shows doubleword mode. addresses are a1?a-1 for word mode. figure 15. page read timings a21 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
january 23, 2006 am29lv6402m 43 ac characteristics hardware reset (reset#) 1. not 100% tested 2. ac specifications are tested with v io =v cc . please contact the factory for information on using the device with v io v cc . parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 16. reset timings
44 am29lv6402m january 23, 2006 ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 doublewords/1?32 words programmed. 4. effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. ac specifications are tested with v io =v cc . please contact the factory for information on using the device with v io v cc . parameter speed options jedec std. description 100r 110r unit t avav t wc write cycle time (note 1) min 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per word typ 11 s per doubleword typ 22 s accelerated effective write buffer program operation (notes 2, 4) per word typ 8.8 s per doubleword typ 17.6 s single doubleword/word program operation (note 2) word typ 100 s doubleword typ 100 s accelerated single doubleword/word programming operation (note 2) word typ 90 s doubleword typ 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
january 23, 2006 am29lv6402m 45 ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 17. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
46 am29lv6402m january 23, 2006 ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?). 2. these waveforms are for the doubleword mode. figure 19. chip/sector erase operation timings
january 23, 2006 am29lv6402m 47 ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle af ter command sequence, last stat us read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
48 am29lv6402m january 23, 2006 ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6 and dq14. illustrati on shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 and dq10 toggle only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq1- and dq6 and dq14. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq2, erase complete erase suspend suspend program resume embedded erasing dq6, dq14 dq10
january 23, 2006 am29lv6402m 49 ac characteristics temporary sector unprotect 1. not 100% tested. 2. ac specifications are tested with v io =v cc . please contact the factory for information on using the device with v io v cc . parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time fo r temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 23. temporary sector group unprotect timing diagram
50 am29lv6402m january 23, 2006 ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 24. sector group protect and unprotect timing diagram
january 23, 2006 am29lv6402m 51 ac characteristics alternate ce# cont rolled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 doublewords/1?32 words programmed. 4. effective write buffer specification is based u pon a 16-doubleword/32-word write buffer operation. 5. ac specifications are tested with v io =v cc . please contact the factory for information on using the device with v io v cc . parameter speed options jedec std. description 100r 110r unit t avav t wc write cycle time (note 1) min 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 352 s effective write buffer program operation (notes 2, 4) per word typ 11 s per doubleword typ 22 s effective accelerated write buffer program operation (notes 2, 4) per word typ 8.8 s per doubleword typ 17.6 s single doubleword/word program operation (note 2) word typ 100 s doubleword typ 100 s accelerated single doubleword/word programming operation (note 2) word typ 90 s doubleword typ 90 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec
52 am29lv6402m january 23, 2006 ac characteristics latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# and dq15# are the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 25. alternate ce# controlled write (erase/program) operation timings description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
january 23, 2006 am29lv6402m 53 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is based u pon a 16-doubleword/32-word write buffer operation. 4. for 1?16 doublewords or 1-32 words programmed in a single write buffer programming operation. 5. in the pre-programming step of the embedded erase al gorithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see tables 10 and 11 for further information on command definitions. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec excludes 00h programming prior to erasure (note 5) chip erase time 32 128 sec single doubleword/word program time (note 3) word 100 tbd s excludes system level overhead (note 6) doubleword 100 tbd s accelerated single doubleword/ word program time word 90 tbd s doubleword 90 tbd s total write buffer program time (note 4) 352 tbd s effective write buffer program time (note 3) per word 11 tbd s per doubleword 22 tbd s total accelerated write buffer program time (note 4) 282 tbd s effective write buffer accelerated program time (note 3) per word 8.8 tbd s per doubleword 17.6 tbd s chip program time 92 tbd sec parameter symbol parameter desc ription test setup typ max unit c in input capacitance v in = 0 bga tbd tbd pf c out output capacitance v out = 0 bga tbd tbd pf c in2 control pin capacitance v in = 0 bga tbd tbd pf parameter description t est conditions min unit minimum pattern data retention time 150c 10 years 125c 20 years
54 am29lv6402m january 23, 2006 physical dimensions lsb080?80-ball fortified ball grid array (fortified bga) 13 x 11 mm package 3265 \ 16-038.15a package lsb 080 jedec n/a d x e 13.00 mm x 11.00 mm package symbol min nom max note a --- --- 1.60 profile a1 0.40 --- --- ball height a2 1.00 --- 1.11 body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 9.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.50 0.60 0.70 ball diameter ee 1.00 bsc. ball pitch ed 1.00 bsc ball pitch sd / se 0.50 bsc. solder ball placement depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 80x c 0.20 (2x) (2x) c 0.20 b a 6 b 0.25 c c 0.25 m c mc ab 0.10 d e c top view side view a2 a1 a 0.20 10 index mark corner pin a1 bottom view kj ed corner e1 7 se d1 a b dc e f hg 8 7 5 6 4 2 3 1 ee sd pin a1 7
january 23, 2006 am29lv6402m 55 revision summary revision a (january 20, 2003) initial release. revision b (septe mber 17, 2003) global changed data sheet status from advance information to preliminary. distinctive characteristics changed description of device erase cycle endurance. changed typical sector erase time, typical write buffer programming time, and typical active read current specification. customer lockable: secsi sector not programmed or protected at the factory. added second bullet, secsi sector-protect verify text and figure 3. erase suspend/erase resume commands deleted reference to erase-suspended sector address requirement for commands. tables 10 and 11, command definitions corrected addresses for erase suspend and erase resume to ?xxx? (don?t care). dc characteristics changed typical and maximum values for i cc1 , i cc2 , and i cc3 . values for different frequencies were added to i cc2 and i cc3 . ac characteristics erase and program operations table; alternate ce# controlled erase and program operations table. changed values for the following parameters: write buffer program operation, effective write buffer pro- gram operation, accelerated effective write buffer program operation, sector erase operation, single doubleword/word program operation, accelerated single doubleword/word program operation (the phrase ?single doubleword/word? was added to the last two parameter titles). erase and programming performance changed typical sector erase time. changed typical chip erase time and added maximum erase time. re- placed tbds for all typical specifications with actual values. added phrase ?single doubleword/word? to program time and accelerated program time param- eters titles. added total write buffer program time and total accelerated write buffer program time pa- rameters to table. changed device endurance in note 1 to 10,000 cycles. changed write buffer operation size in note 3. note 4 now refers to write buffer pro- gramming instead of chip programming. deleted note 7. revision b+1 (january 23, 2006) this product has been retired and is not available for designs. for new and current designs, s29gl128n supersedess29lv6402m and is the factory-recom- mended migration path. please refer to the s29gl128n data sheet for specifications and order- ing information. availability of this document is re- tained for reference and historical purposes only. updated migration statement on cover page and first page of data sheet. updated trademarks. trademarks copyright ? 2005-2006 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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